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Tricks on passing macro to make command in terminal  

2017-02-02 21:52:19|  分类: 编程技巧合集 |  标签: |举报 |字号 订阅

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After writing so much codes/projects, we all know the usefuless of using macro(s) to control the compilations (in C/C++ and fortran, may be more other languages?).  Makefile is a script that records what we want the project to be compiled, and in which one can define as many as possible macros that could be passed to the compiler, i.e., something like $(CC) $(CPPFLAG).

Sometimes, I got tired of modifying the makefile. Then how can I do without modifying the makefile but still pass some macros to the compiler? The answer is quite simple, see the example below:

now suppose we have a flag in the makefile, for example, CCFLAG.  This flag can be given a empty value, or simply to say don't give it a value.  The existence of the value is irrelevant.  Now we work in a terminal, and we are ready to type "make" to start the compilation.  But inside the code I have used a macro, for example,
#ifdef _COMPILE_ME_
// some codes
#endif
and I want the compiler know that "_COMPILER_ME_" is defined (but not inside the makefile),  I just need to use the following compound command:
make CCFLAG=-D_COMPILER_ME_
the value, if any, of CCFLAG inside the makefile will be over-written.

Isn't that simple?
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